(1) Field of the Invention
This invention relates to methods of preserving alignment marks in integrated circuit substrates and more particularly to preserving alignment marks in methods using shallow trench isolation and chemical mechanical polishing.
(2) Description of the Related Art
U.S. Pat. No. 5,266,511 to Takao describes forming an alignment mark on the top surface of a first substrate which has been covered with a first insulating layer and planarized. The alignment mark is located in the scribe line area. A second substrate is provided with a groove corresponding to the scribe line area having the alignment mark. The two substrates are brought together in facing contiguous relationship and bonded together using an infrared microscope to align the groove to the alignment mark.
U.S. Pat. No. 5,401,691 to Caldwell describes a method of forming an alignment mark during semiconductor device manufacturing. The method uses a first area and a second area provided on a semiconductor substrate with the first area adjacent to the second area. The invention describes the formation of an alignment mark using an inverse open frame.
U.S. Pat. No. 5,627,110 to Lee et al. describes a method of exposing an alignment mark without the need to use additional mask process.
A patent application TSMC-97-354 Ser. No. 09/135,043 Filed Aug. 17, 1998, entitled "REGENERATION OF ALIGNMENT MARKS AFTER SHALLOW TRENCH ISOLATION WITH CHEMICAL MECHANICAL POLISHING" and assigned to the same assignee describes methods of preserving alignment marks in integrated circuit substrates.